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Changes of Revision 9
View file
_service:tar_scm_kernel_repo:coreutils.spec
Changed
@@ -1,6 +1,6 @@ Name: coreutils Version: 9.0 -Release: 5 +Release: 6 License: GPLv3+ Summary: A set of basic GNU tools commonly used in shell scripts Url: https://www.gnu.org/software/coreutils/ @@ -24,6 +24,9 @@ Patch10: backport-coreutils-i18n.patch Patch11: backport-sort-fix-sort-g-infloop-again.patch Patch12: backport-tests-sort-NaN-infloop-augment-testing-for-recent-fi.patch +%ifarch sw_64 +Patch13: coreutils-9.0-sw.patch +%endif Conflicts: filesystem < 3 # To avoid clobbering installs @@ -145,6 +148,9 @@ %{_mandir}/man*/* %changelog +* Wed Oct 19 2022 wuzx<wuzx1226@qq.com> - 9.0-6 +- add sw64 patch + * Sat Aug 27 2022 zoulin <zoulin13@h-partners.com> - 9.0-5 - fix 'sort -g' don't meet expectations
View file
_service:tar_scm_kernel_repo:coreutils-9.0-sw.patch
Added
@@ -0,0 +1,233 @@ +diff -Nuar coreutils-9.0.org/build-aux/config.guess coreutils-9.0.sw/build-aux/config.guess +--- coreutils-9.0.org/build-aux/config.guess 2022-02-17 15:38:25.880000000 +0000 ++++ coreutils-9.0.sw/build-aux/config.guess 2022-02-17 16:03:14.150000000 +0000 +@@ -973,6 +973,14 @@ + UNAME_MACHINE=aarch64_be + GUESS=$UNAME_MACHINE-unknown-linux-$LIBC + ;; ++ sw_64:Linux:*:*) ++ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null` in ++ sw) UNAME_MACHINE=sw_64 ;; ++ esac ++ objdump --private-headers /bin/sh | grep -q ld.so.1 ++ if test "$?" = 0 ; then LIBC=gnulibc1 ; fi ++ GUESS=$UNAME_MACHINE-sunway-linux-$LIBC ++ ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null` in + EV5) UNAME_MACHINE=alphaev5 ;; +diff -Nuar coreutils-9.0.org/build-aux/config.sub coreutils-9.0.sw/build-aux/config.sub +--- coreutils-9.0.org/build-aux/config.sub 2022-02-17 15:38:25.880000000 +0000 ++++ coreutils-9.0.sw/build-aux/config.sub 2022-02-17 16:03:30.560000000 +0000 +@@ -1177,6 +1177,7 @@ + | a29k \ + | aarch64 | aarch64_be \ + | abacus \ ++ | sw_64 \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \ + | alphapca5[67] | alpha64pca5[67] \ +diff -Nuar coreutils-9.0.org/configure coreutils-9.0.sw/configure +--- coreutils-9.0.org/configure 2022-02-17 15:38:26.280000000 +0000 ++++ coreutils-9.0.sw/configure 2022-02-17 15:58:05.480000000 +0000 +@@ -7845,6 +7845,12 @@ + # (according to the test results of Bruno Haible's ieeefp/fenv_default.m4 + # and the GCC 4.1.2 manual). + case "$host_cpu" in ++ sw_64*) ++ if test -n "$GCC"; then ++ # GCC has the option -mieee. ++ CPPFLAGS="$CPPFLAGS -mieee" ++ fi ++ ;; + alpha*) + # On Alpha systems, a compiler option provides the behaviour. + # See the ieee(3) manual page, also available at +@@ -18808,7 +18814,7 @@ + case "$gl_cv_host_cpu_c_abi" in + i386 | x86_64-x32 | arm | armhf | arm64-ilp32 | hppa | ia64-ilp32 | mips | mipsn32 | powerpc | riscv*-ilp32* | s390 | sparc) + gl_cv_host_cpu_c_abi_32bit=yes ;; +- x86_64 | alpha | arm64 | hppa64 | ia64 | mips64 | powerpc64 | powerpc64-elfv2 | riscv*-lp64* | s390x | sparc64 ) ++ x86_64 | sw_64 | alpha | arm64 | hppa64 | ia64 | mips64 | powerpc64 | powerpc64-elfv2 | riscv*-lp64* | s390x | sparc64 ) + gl_cv_host_cpu_c_abi_32bit=no ;; + *) + gl_cv_host_cpu_c_abi_32bit=unknown ;; +@@ -18837,7 +18843,7 @@ + ;; + + # CPUs that only support a 64-bit ABI. +- alpha | alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] \ ++ sw_64* | alpha | alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] \ + | mmix ) + gl_cv_host_cpu_c_abi_32bit=no + ;; +diff -Nuar coreutils-9.0.org/lib/uname.c coreutils-9.0.sw/lib/uname.c +--- coreutils-9.0.org/lib/uname.c 2022-02-17 15:38:26.740000000 +0000 ++++ coreutils-9.0.sw/lib/uname.c 2022-02-17 15:59:09.500000000 +0000 +@@ -228,6 +228,10 @@ + case PROCESSOR_ARCHITECTURE_MIPS: + strcpy (buf->machine, "mips"); + break; ++ case PROCESSOR_ARCHITECTURE_SW_64: ++ case PROCESSOR_ARCHITECTURE_SW_6464: ++ strcpy (buf->machine, "sw_64"); ++ break; + case PROCESSOR_ARCHITECTURE_ALPHA: + case PROCESSOR_ARCHITECTURE_ALPHA64: + strcpy (buf->machine, "alpha"); +diff -Nuar coreutils-9.0.org/m4/fpieee.m4 coreutils-9.0.sw/m4/fpieee.m4 +--- coreutils-9.0.org/m4/fpieee.m4 2022-02-17 15:38:25.890000000 +0000 ++++ coreutils-9.0.sw/m4/fpieee.m4 2022-02-17 15:41:57.490000000 +0000 +@@ -30,6 +30,12 @@ + # (according to the test results of Bruno Haible's ieeefp/fenv_default.m4 + # and the GCC 4.1.2 manual). + case "$host_cpu" in ++ sw_64*) ++ if test -n "$GCC"; then ++ # GCC has the option -mieee. ++ CPPFLAGS="$CPPFLAGS -mieee" ++ fi ++ ;; + alpha*) + # On Alpha systems, a compiler option provides the behaviour. + # See the ieee(3) manual page, also available at +diff -Nuar coreutils-9.0.org/m4/host-cpu-c-abi.m4 coreutils-9.0.sw/m4/host-cpu-c-abi.m4 +--- coreutils-9.0.org/m4/host-cpu-c-abi.m4 2022-02-17 15:38:25.900000000 +0000 ++++ coreutils-9.0.sw/m4/host-cpu-c-abi.m4 2022-02-17 15:41:29.970000000 +0000 +@@ -91,6 +91,12 @@ + ;; + + changequote(,)dnl ++ sw_64* ) ++changequote([,])dnl ++ gl_cv_host_cpu_c_abi=sw_64 ++ ;; ++ ++changequote(,)dnl + alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] ) + changequote([,])dnl + gl_cv_host_cpu_c_abi=alpha +@@ -355,6 +361,9 @@ + #ifndef __x86_64__ + #undef __x86_64__ + #endif ++#ifndef __sw_64__ ++#undef __sw_64__ ++#endif + #ifndef __alpha__ + #undef __alpha__ + #endif +@@ -468,7 +477,7 @@ + case "$gl_cv_host_cpu_c_abi" in + i386 | x86_64-x32 | arm | armhf | arm64-ilp32 | hppa | ia64-ilp32 | mips | mipsn32 | powerpc | riscv*-ilp32* | s390 | sparc) + gl_cv_host_cpu_c_abi_32bit=yes ;; +- x86_64 | alpha | arm64 | hppa64 | ia64 | mips64 | powerpc64 | powerpc64-elfv2 | riscv*-lp64* | s390x | sparc64 ) ++ x86_64 | sw_64 | alpha | arm64 | hppa64 | ia64 | mips64 | powerpc64 | powerpc64-elfv2 | riscv*-lp64* | s390x | sparc64 ) + gl_cv_host_cpu_c_abi_32bit=no ;; + *) + gl_cv_host_cpu_c_abi_32bit=unknown ;; +@@ -498,7 +507,7 @@ + + # CPUs that only support a 64-bit ABI. + changequote(,)dnl +- alpha | alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] \ ++ sw_64* | alpha | alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] \ + | mmix ) + changequote([,])dnl + gl_cv_host_cpu_c_abi_32bit=no +diff -Nuar coreutils-9.0.org/src/longlong.h coreutils-9.0.sw/src/longlong.h +--- coreutils-9.0.org/src/longlong.h 2022-02-17 15:38:26.750000000 +0000 ++++ coreutils-9.0.sw/src/longlong.h 2022-02-17 15:55:26.520000000 +0000 +@@ -170,6 +170,92 @@ + don't need to be under !NO_ASM */ + #if ! defined (NO_ASM) + ++#if defined (__sw_64) && W_TYPE_SIZE == 64 ++/* Most sw_64-based machines, except Cray systems. */ ++#if defined (__GNUC__) ++#if __GMP_GNUC_PREREQ (3,3) ++#define umul_ppmm(ph, pl, m0, m1) \ ++ do { \ ++ UDItype __m0 = (m0), __m1 = (m1); \ ++ (ph) = __builtin_sw_64_umulh (__m0, __m1); \ ++ (pl) = __m0 * __m1; \ ++ } while (0) ++#else ++#define umul_ppmm(ph, pl, m0, m1) \ ++ do { \ ++ UDItype __m0 = (m0), __m1 = (m1); \ ++ __asm__ ("umulh %r1,%2,%0" \ ++ : "=r" (ph) \ ++ : "%rJ" (__m0), "rI" (__m1)); \ ++ (pl) = __m0 * __m1; \ ++ } while (0) ++#endif ++#else /* ! __GNUC__ */ ++#include <machine/builtins.h> ++#define umul_ppmm(ph, pl, m0, m1) \ ++ do { \ ++ UDItype __m0 = (m0), __m1 = (m1); \ ++ (ph) = __UMULH (__m0, __m1); \ ++ (pl) = __m0 * __m1; \ ++ } while (0) ++#endif ++#ifndef LONGLONG_STANDALONE ++#define udiv_qrnnd(q, r, n1, n0, d) \ ++ do { UWtype __di; \ ++ __di = __MPN(invert_limb) (d); \ ++ udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \ ++ } while (0) ++#define UDIV_PREINV_ALWAYS 1 ++#define UDIV_NEEDS_NORMALIZATION 1 ++#endif /* LONGLONG_STANDALONE */ ++ ++/* clz_tab is required in all configurations, since mpn/sw_64/cntlz.asm ++ always goes into libgmp.so, even when not actually used. */ ++#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB ++ ++#if defined (__GNUC__) && HAVE_HOST_CPU_sw_64_CIX ++#define count_leading_zeros(COUNT,X) \ ++ __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X)) ++#define count_trailing_zeros(COUNT,X) \ ++ __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X)) ++#endif /* clz/ctz using cix */ ++ ++#if ! defined (count_leading_zeros) \ ++ && defined (__GNUC__) && ! defined (LONGLONG_STANDALONE) ++/* SW_64_CMPBGE_0 gives "cmpbge $31,src,dst", ie. test src bytes == 0. ++ "$31" is written explicitly in the asm, since an "r" constraint won't ++ select reg 31. There seems no need to worry about "r31" syntax for cray,
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